Understanding PCIe Transaction Layer
1. IntroductionPCI Express (PCIe) is designed as a layered architecture to separate concerns such as packet generation, reliability, and physical transmission. Among these layers, theTransaction Layerplays a. . .
1. IntroductionPCI Express (PCIe) is designed as a layered architecture to separate concerns such as packet generation, reliability, and physical transmission. Among these layers, theTransaction Layerplays a central role by translating software-level operations into structured packets that traverse the PCIe fabric. This article presents a structured explanation of the Transaction Layer, focusing on its responsibilities, transaction types, and the detailed structure of Transaction Layer Packets (TLPs). 2. PCIe LayersTransaction Layer (TL):Generates Transaction Layer Packets (TLPs)Data Link Layer (DLL):Ensures reliable delivery of TLPs across a linkPhysical Layer (PHY):Handles electrical signaling and bit-level transmission3. Role of Transaction LayerThe responsibilities listed below correspond to theTransaction Layer:Determines the destination using memory address or ID-based routingConverts read/write/configuration requests intoTransaction Layer Packets (TLPs)4. Types of PCIe TransactionsPCIe defines multiple transaction types:Memory TransactionsMemory ReadMemory WriteConfiguration TransactionsUsed during device enumerationAccess configuration spaceMessage TransactionsInterrupts (MSI/MSI-X)Power managementError signalingCompletion TransactionsResponses to requests (e. g. , returning data for a read request)5. Transaction Layer Packet (TLP) StructureA TLP is the fundamental unit of communication in PCIe. +---------------------------------+ | TLP Header (3DW / 4DW) | +---------------------------------+ | Data Payload (optional) | +---------------------------------+ | Digest (optional) | +---------------------------------+Enter fullscreen modeExit fullscreen mode5. 1 TLP HeaderThe TLP header defines the type, intent, and routing information of the packet. DW0 — Format and Control:31 24 23 20 19 16 15 0 +--------------+---------+---------+------------------+ | Fmt + Type | TC | Attr | Length | +--------------+---------+---------+------------------+Enter fullscreen modeExit fullscreen modeKey DW0 fields:Fmt (Format): 3 bits. Indicates header size (3DW or 4DW) and whether a data payload is present. 000= 3-DW header, no data (e. g. , 32-bit Memory Read)001= 4-DW header, no data (e. g. , 64-bit Memory Read)010= 3-DW header, with data (e. g. , 32-bit Memory Write)011= 4-DW header, with data (e. g. , 64-bit Memory Write)Type: 5 bits. Combined with Fmt, defines the TLP type:00000= Memory Read Request (MRd)00001= Memory Read Request Locked (MRdLk)00000with Fmt010= Memory Write (MWr)00100= Configuration Read Type 0 (CfgRd0)00101= Configuration Write Type 0 (CfgWr0)01010= Completion (Cpl)01010with Fmt010= Completion with Data (CplD)10000= Message Request (Msg)TC (Traffic Class): 3 bits. Indicates priority (0–7). Most traffic uses TC0. Length: 10 bits. Specifies the number of DWORDs in the data payload (1–1024). A value of 0 represents 1024 DWORDs. DW1 — Request Identification:31 16 15 8 7 4 3 0 +------------------+----------+-----------+-----------+ | Requester ID | Tag | Last BE | First BE | +------------------+----------+-----------+-----------+Enter fullscreen modeExit fullscreen modeKey DW1 fields:Requester ID: 16 bits. Identifies the source device using Bus/Device/Function (BDF). Bus Number (8 bits) | Device Number (5 bits) | Function Number (3 bits)Enter fullscreen modeExit fullscreen modeTag: 8 bits. A unique identifier assigned by the requester. Used to match Completion TLPs with their corresponding requests. Last Byte Enable (Last BE): 4 bits. Indicates valid bytes in the last DWORD of the payload. Relevant for unaligned or partial transfers. First Byte Enable (First BE): 4 bits. Indicates valid bytes in the first DWORD of the payload. Example (partial write):Write 6 bytes starting at an offset within a DWORD:DWORD N: +----+----+----+----+ | B3 | B2 | B1 | B0 | +----+----+----+----+ ✔ ✔ ✔ ✘ → First BE = 1110 DWORD N+1: +----+----+----+----+ | B3 | B2 | B1 | B0 | +----+----+----+----+ ✘ ✔ ✔ ✔ → Last BE = 0111Enter fullscreen modeExit fullscreen modeDW2/DW3 — Address:Contains the target address for Memory transactionsDW2: Lower 32 bits of addressDW3: Upper 32 bits (used only for 64-bit addressing)